1. Field of the Invention
This invention relates generally to hard disk error correction code decoders, and more particularly to devices for extending error correction beyond a sector time.
2. Description of the Related Art
Modem computer systems typically include one or more hard disk drives to store large amount of data and programs. As a mass storage device, hard disk drives can provide information to the processors in the computer systems through random access memory (RAM) circuitry such as dynamic random access memory (DRAM), static random access memory (SRAM), etc. Since RAM circuitry is costly, storing information in a hard disk and retrieving the information as needed is generally far more economical than using comparable RAM circuitry for most computer applications.
Hard disk drives typically store information in sequence by using magnetic technology. Like most recording technology, reading the sequential data bits from a hard disk often generates errors due to noise, manufacturing imperfections of the physical medium, dust, etc. To detect and correct such errors, hard disk drives typically implement an error correction code (ECC) scheme in writing to and reading from hard disk drives.
Conventional ECC devices and methods typically employ well known codes such as Reed-Solomon code to encode user data for reliable recovery of the original data. Modern hard disk drives generally employ Reed-Solomon error correction code for correcting burst errors. This helps to achieve a higher areal density.
Traditional ECC schemes typically compute ECC bytes for a given block of user data such as a sector. Then, the computed ECC bytes are appended to the sector of user data and then recorded on a hard disk medium. Each sector typically contains 512 bytes of user data and additional ECC check bytes appended to the user data bytes. Each sector includes a sync pattern or bytes for identifying the beginning of the sector. The sync pattern or bytes are thus used to delineate a sector boundary. When the recorded sectors of data are read from the hard disk, the ECC scheme decodes the received sector data including the ECC bytes by generating syndromes for the received data in each of the sectors. Zero syndromes indicate that no error has been detected in the sector while non-zero syndromes indicate that one or more errors have been detected in the sector. For each of the sectors with non-zero syndromes, error locations and error patterns are determined and based on these information, the detected errors in the sector are corrected.
In conventional ECC devices, when data is read off from hard disk media, the data are typically stored in a temporary buffer for error detection and correction. During this time, on-the-fly error correction is performed on the data in the temporary buffer. To keep data flow uninterrupted, traditional ECC devices generally implement a high level pipeline scheme where sectors are continuously read and processed. That is, after sector 1 is placed in the temporary buffer, sector 2 is continuously read while error correction is performed on the data held in the temporary buffer. After errors, if any, have been detected and corrected, the data in the buffer is transferred to a host computer.
Given this constraint, conventional ECC devices and methods have typically required that the latency of error correction performed on any given sector be completed within one sector time, i.e., the time it takes to read or receive a sector. Prior Art FIG. 1 illustrates a block diagram of a conventional computer system 100 including a host computer 114 and a hard disk drive (HDD) 102. The host computer is coupled to the hard disk drive 102 to receive user or ECC decoded data. The hard disk drive 102 includes hard disk media 106, a hard disk controller (HDC) 104, and a buffer 112.
In this configuration, data stored in the sectors (e.g., S1, S2, S3, S4, and so on) are read sequentially as a data stream from the hard disk media 106 and transmitted to the hard disk controller 104. The hard disk controller 104 includes a disk manager 108 and an ECC decoder 110. The disk manager 108 sequentially receives the serial data and converts (e.g., deserialize) the data into a series of sectors (e.g., S1, S2, S3, S4, and so on), each of which typically contains 512 bytes of user data and additional ECC bytes appended to the user data bytes. In particular, the disk manager 108 detects sync pattern or bytes to identify or delineate each of the sectors sequentially from the received data stream. The disk manager 108 then transmits the sector data of the identified sector sequentially to the ECC decoder 110 and the buffer 112 concurrently. The ECC decoder 110 generates syndromes for the identified sector on-the-fly. The buffer 112 stores the sector data as the ECC decoder 110 is generating syndromes.
As defined herein, the time it takes to receive an entire sector in the buffer 112 is referred to as a "sector time." One sector time can also refer to the time for the ECC decoder 110 to receive data and generate syndromes for the identified sector. For real time or on-the-fly error correction, these two sector times will typically be the same. In this manner, when the ECC decoder 110 has finished generating the syndromes for the current sector, the it can determine error locations and patterns to correct detected errors, if any, in the current sector stored in the buffer 112 while the next sector is being received. After determining the error locations and patterns, the ECC decoder 110 corrects the errors in the stored data in the buffer 112 using the error locations and error patterns. The corrected data is then transmitted to the host computer 114.
For example, the ECC decoder 110 receives sector S1 from the disk manager 108 and generates syndromes for sector S1 during one sector time. The buffer 112 concurrently receives and stores sector S1. Upon receiving all the data for sector S1, the ECC decoder 110 receives the next sector S2 and generates the associated syndromes. The buffer 112 concurrently receives and stores sector S2. While receiving next sector S2, the ECC decoder 110 generates error patterns (i.e., values) and locations and performs error correction on received sector S1 stored in the buffer 112. To ensure sustained data flow, the error correction on sector S1 is typically limited to one sector time.
However, if error correction does not complete within one sector time, an error condition is generated indicating error correction overrun. For example, in ECC schemes, it is often desirable to implement a higher correction power by increasing the number of errors detected and corrected. Unfortunately, as the desired ECC correction power increases, the time for the ECC decoder 108 to process an ECC algorithm will likely increase. Further, the higher correction power will typically require more data access to the buffer 112, resulting in further delays. In addition, the buffer 112 often is not dedicated to the exclusive use of the ECC decoder 108. For example, the buffer 112 can be shared among multiple ports such as the host computer 114, the hard disk drive 102, dynamic random-access-memory (DRAM) refresh, etc.
When the bandwidth requirements increase on a host bus and hard disk data transfer rate, the buffer bandwidth may become a bottleneck for the ECC decoder 112. In these cases, the error correction in the buffer 112 typically may not be completed within one sector time. When the error correction thus extends beyond the allocated one sector time, the data transfer is interrupted since the ECC decoder 110 is no longer capable of handling sustained data flow. In these instances, the hard disk controller 104 generates an error event often called "correction overrun" and stops reading data from the hard disk media 106. The hard disk controller 104 may then process the error and re-read the interrupted sector by waiting for the hard disk media 106 to make another revolution to the beginning of the sector. Such interruption of data flow thus causes undesirable delays and performance penalties.
One solution to this problem is to implement an ultra fast ECC decoder to ensure that the worst case buffer access latency is within the allotted one sector time. This approach, however, would require complex and expensive hardware resources for implementing the ECC decoder. Another solution may be to integrate an on-chip sector buffer so that error correction on an external buffer is eliminated. However, the on-chip sector buffer solution would require, among other circuitry, at least two costly dedicated sector buffers.
Thus, what is needed is a cost effective device and method that can extend error correction beyond a sector time without interrupting data flow. What is further needed is an extended error correction device and method that can be implemented without integrating costly hardware resources.